Delay locked loops (DLLs) are often used in integrated circuits (ICs) to generate an internal clock signal. In a typical DLL, the internal clock signal is generated by applying a delay to a system clock or an external clock signal. The DLL automatically adjusts the delay to keep the internal and external clock signals synchronized.
In some integrated circuit devices, such as dynamic random access memory (DRAM) devices, a DLL is normally used to provide a timing signal for certain operations of the memory device. For example, in some memory devices, the internal clock signal generated by the DLL can be used as capture clock signal, or a strobe signal during a READ or a WRITE mode.
A traditional memory device has a number of memory cells to store data. To retrieve the stored data, a READ mode is performed. Typically, the READ mode includes two steps. First, the memory device activates a so-called ACTIVE command signal during an ACTIVE mode to “open” or activate the memory cells. Next, a READ command signal is activated to access the memory cells to read the stored data. In the traditional memory device, activating the memory cells during the ACTIVE mode demands a high amount of current. This causes the supply voltage of the memory device to drop. The drop in the supply voltage changes the voltage supplied to the DLL of the memory device. The change in the voltage supply of the DLL causes the external and internal clock signals to be out of synchronism.
The DLL attempts to keep the internal and external clock signals synchronized by adjusting the delay to compensate for any variation in operating conditions such as the drop in the supply voltage. Reducing the effect of the change in operating conditions of the DLL such as the voltage drop during the ACTIVE mode is desirable.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved DLL.